This invention relates to a signal propagating device having at least one interconnection layer formed of a resistive material.
In a memory device having a plurality of memory cells, the operation of writing and reading data to and from each memory cell is usually controlled by a control signal propagating through a word line. The word line is usually formed of a polycrystalline silicon interconnection layer having resistivity (of about 30.OMEGA./.quadrature.) in order to prevent interference with aluminum interconnection layers formed in the individual cells. This kind of polycrystalline silicon interconnection layer is designed to have a smaller total width and a larger total length in order to reduce the dimensions of circuit elements in a memory and also increase the storage capacity of the memory. For this reason, the lead resistance is extremely increased, to as high as 10 k.OMEGA., for instance. In another aspect, some portions of the polycrystalline silicon interconnection layer are also used as gate electrodes of MOS transistors constituting memory cells, so that the polycrystalline silicon interconnection layer will be accompanied by large parasitic capacitances. Therefore, a control signal propagated through the polycrystalline silicon interconnection layer is extremely delayed, having increased the time required for making access the memory circuit. In order to reduce the control signal propagation delay, it has been proposed to form the word line with a material having very low resistivity and good conductivity such as molybdenum silicide (MoSi.sub.2) instead of the polycrystalline silicon interconnection layer. However, this has not yet been put into practice because there are many technical problems unresolved.
FIG. 1 shows a prior art signal propagating device. A word line 2 of a polycrystalline silicon layer is formed on a plurality of memory cell regions MC-1 to MC-N arranged in a chain. A control signal propagated along the word line 2 is supplied to memory cells formed in the individual memory cell regions. Since the word line 2 is also used as a gate of the MOS transistor constituting each memory cell, the word line cannot be formed to have a uniform width, but it is formed to have an equal average width for the individual memory cell regions. Where the sheet resistance of the polycrystalline silicon layer constituting the word line 2 is denoted by .rho., the capacitance per unit area of the layer by CO and the average width and length of the word line respectively by W and 2L, the resistance of the whole word line is given as .rho..multidot.2L/W and the capacitance accompanying the word line is given as 2L.multidot.W.multidot.CO. Suppose now that the word line 2 includes two equal sections as shown in FIG. 2. In other words, suppose a circuit where resistors R1 and R2 are respectively connected between points P1 and P2 and between points P2 and P3 and capacitors C1 and C2 are connected to the respective points P2 and P3. The resistance of each of the resistors R1 and R2 is .rho.(L/W) (=R), and the capacitance of each of the capacitors C1 and C2 is L.multidot.W.multidot.CO (=C). Then, if there is no voltage signal applied to the point P1, there holds a relation VA=VB=VC where VA, VB and VC are respectively the potentials on the points P1, P2 and P3. When a voltage signal with a voltage level of VO is applied to the point P1 at an instant t=0, the differentials dVB/dt and dVC/dt of the potentials VB and VC are given as ##EQU1## and ##EQU2##
By substituting an initial condition of VB=VC=0 at t=0 into the equations (1) and (2), we obtain equations ##EQU3## and ##EQU4##
FIG. 3 shows the potentials VB and VC in the equations (3) and (4) plotted against the time constant t/CR. As is seen, the potential VC at the point C, farther from the point A than the point B, rises more slowly than the potential VB at the point B. In other words, the delay time of the signal propagated through the circuit path is increased with increasing distance from the point of signal application.